| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === In most radio frequency (RF) communication systems, frequency synthesizers are utilized to implement the frequency up/down converting of signal. Voltage Controlled Oscillator (VCOs) and Injection Locked Frequency Doublers (ILFDs) are common functional blocks of frequency synthesizers. The VCO is to generate the local frequency signal and modulating or demodulating the RF signal. A good VCO must exhibit a low phase-noise output to avoid corrupting the mixer-converted signal by close interfering tones and a wide operation range to be potentially resistant to process, voltage and temperature variation. To the ILFD, it should have the ability to work at high frequency and in a broad locking range of frequency. Low power dissipation is another challenging requirement in the design of VCO and ILFD due to the battery lifetime. In this thesis, we propose three VCOs and ILFD which have been successfully implemented.
The first VCO is a 10-GHz push-push differential VCO with the current-reuse technique. It is implemented with TSMC 0.18 μm CMOS technology. The push-push doubler is used to convert quadrature output signal of QVCO to differential signal so that the VCO can operate at higher frequency. The CMOS VCO dissipates only 3.15 mW at the supply voltage of 0.9 V due to applied current-reuse technique. The best phase noise of this VCO is -114.93 dBc/Hz at 1 MHz offset frequency. The figure of merit (FOM) is -190dBc/Hz and the VCO achieves the tuning range of 11% from 10 to 11.15 GHz.
A dual cross-coupled n-core CMOS VCO is also presented. It was fabricated in the standard TSMC 0.18 μm SiGe process. Measurement result proves the proposed structure offers many considerable advantages - high performance, low power consumption, wide tuning range. The proposed circuit has low-power consumption of 3.2 mW at the supply voltage of 0.65V, and a small size area - 0.698x0.654mm2. The operating frequency of the VCO can be tuned from 3.97 to 5.3 GHz while the tuning voltage varies from 0 to 1.6 V. The phase noise of the proposed circuit is -123.95 dBc/Hz at 1 MHz frequency offset. The calculated FOM is -190.82dBc/Hz.
The next proposed circuit is a single-ended ILFD based on Colpitts-Armstrong structure. The ILFD consists of a push-push doubler cascaded by injection-locked oscillator (ILO) to provide large output swing and also as a filter to the undesired harmonics. The proposed ILFD operates at 2.1V supply voltage and consumes the power of 7.14 mW. It provides a wide locking range from 2.4 to 2.81 GHz (15.7%). Good phase noise performance is measured in injection-locked state.
The last circuit presented in this thesis is a dual-resonance VCO implemented in TSMC 0.18 μm CMOS technology. The dual-resonance LC resonator comprises two parallel-tuned LC resonators at different resonance frequencies in series. With this structure, the operation frequency of the VCO can be switched between two different frequency bands by varying the tuning voltage. Working at the supply voltage of 0.51V, the proposed VCO shows the phase noise of -118.76 (-122.37) dBc/Hz at 1MHz offset frequency from the oscillation frequency of 7.86 (3.61) GHz.
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