| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 100 === In this thesis, we will present two power amplifiers using CMOS processes. These designs based on two different criteria, which are quiescent dc power reduction and high
output power delivery.
The V-band power amplifier using 90-nm CMOS LP process is designed with the adaptive bias circuit based on envelope detector architecture to control the dc power. Two
versions power amplifiers are demonstrated, which are with and without adaptive bias circuit. The measured small signal gain of the PA without adaptive bias is 16 dB. Measured saturation power is 13.8 dBm with peak PAE 13.5% and the OP 1dB is 10.3 dB with PAE 7.3%. In another version, the measured small signal gain of the PA with adaptive bias is 12.7 dB, which saturation power is 12.3 dBm. The OP 1dB is 10.7 dBm with PAE 8.3%. With adaptive bias technique, about 57.6% quiescent dc power consumption can be reduced from 168.6 mW to 72 mW, and the efficiency is also improved in low power operation.
The W-wand power amplifier for high output power is presented in 65-nm CMOS process. A design method to realize a large number of transistors combined matching network is proposed to achieve high output power, and several parasitic effects in high dc power operation are also introduced. The power amplifier achieves measured saturation power of 18.3 dBm with peak PAE 9.4%, which OP 1dB is 17.5 dBm and the linear gain is 12.7 dB. To the author’s knowledge, this output power is the highest for CMOS power amplifiers at 94 GHz to date.
These results present that CMOS PAs are still competitive at high frequencies, which are beneficial to integrate systems in CMOS for millimter-wave applications such as active imaging systems and high data-rate wireless communications.
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