Hardware Architecture and Resource Integration for GPS Acquisition

• Main Authors: Sih-Huan Chen, 陳司桓
• Other Authors: 曹恆偉
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/71065798427672010498

碩士 === 國立臺灣大學 === 電信工程學研究所 === 100 === Within global positioning system (GPS) where acquisition is a signal synchronization process, to be more precisely, the purpose of acquisition is finding the code phase and Doppler frequency shift of visible satellites. Huge searching space of acquisition causes high complexity in both operational and hardware aspects. In the other hand, to improve the acquisition detection performance, both coherent and incoherent integration are needed, and these integration schemes induce memory requirement ascension, so the hardware demand is increased even more for acquisition process. In order to reduce the complexity of acquisition process, two hardware resource integration structures are proposed. For a typical practice code phase search in acquisition process, two hardware resources for coherent integration and correlation operation are needed: SRAM for coherent integration and shift register for correlation operation. The main idea of our design is integrating these two hardware resources together, using only one resource to achieve both coherent integration and correlation operation, so the hardware complexity of acquisition can be reduced with NO detection performance degradation. In the thesis, the hardware architectures and corresponding algorithms of the two proposed acquisition structures will be described. Important issues such as acquisition time, operation frequency will be discussed. The detection performance and hardware complexity are simulated and quantitatively analyzed.