Traffic- and Thermal- balanced Adaptive Beltway Routing Algorithm and Architecture Design for Thermal-Aware 3D NoC Systems

碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === In this thesis, we proposed Traffic- and Thermal- balanced Adaptive Beltway Routing (TTABR) algorithm and architecture design for performance reduction due to the traffic load and thermal distribution imbalance in thermal-aware 3D network-on-chip (NoC). The mi...

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Bibliographic Details
Main Authors: Hui-shun Hung, 洪輝舜
Other Authors: An-Yu Wu
Format: Others
Language:en_US
Published: 2012
Online Access:http://ndltd.ncl.edu.tw/handle/53923852880644896642
Description
Summary:碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === In this thesis, we proposed Traffic- and Thermal- balanced Adaptive Beltway Routing (TTABR) algorithm and architecture design for performance reduction due to the traffic load and thermal distribution imbalance in thermal-aware 3D network-on-chip (NoC). The minimal path routing on 3D NoC cause the unbalance traffic load, which also induce the thermal distribution imbalance. To ensure thermal safety and avoid huge performance back-off from the temperature constraint, run time thermal management is required. However the regulation of temperature requires throttling of the near-overheated router, which makes the topology become Non-Stationary Irregular Mesh (NSI-mesh). It still has performance degradation, and the traffic load imbalance gets worse. Hence the thermal distribution might also become worse and trigger more routers to be throttled. We manage to break this loop to get a better performance and stable 3D NoC systems. TTABR aims to balance the lateral traffic load. It has providing the non-minimal path to increase path diversity and using novel cascade routing to heave the lateral traffic. TTABR also proposed to solve the traffic load imbalance in the vertical direction. Based on the experimental results, the proposed routing scheme can significantly improve the performance and balance traffic load. For low cost implementation, we also propose memory reduction techniques, and we gain 2.7x throughput improvement for only 26.7% area overhead. The throughput per area of our proposed algorithm is 2.1x compared to other related work.