The integration of front-end and back-end of layout vs. schematic checker for passive multilayer microwave circuit
碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === This thesis presents a method that can generate connection status of each component and transform circuit layout into circuit netlist. The circuit layout designed by designer will be stored in format of GDII. Then dividing the rectilinear shape in layout into r...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00123806000606566785 |