| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === This thesis focuses on the research of a spread-spectrum method as well as a de-spreading method. Two topics of these chips are named as an all-digital spread-spectrum clock generator with self-calibrated bandwidth and an all-digital de-spreading clock generator for DisplayPort. They are both fabricated in a 0.18um CMOS process and implemented in an all-digital manner. In contrast to those area-consuming analog filter implementation, these proposed circuits implement the necessary filtering function in a digital way, which achieve a low-cost solution owing to the high density of modern CMOS processes.
The first chip is to realize the proposed spread-spectrum method without the accompanist of DSM quantization noise, which based on the frequency transient response of a PLL. In proposed SSCG, division ratio switching has been chosen as a manner to give the PLL loop a frequency step. By selecting a damping ratio properly, the transient frequency will have a triangular profile in time-domain and has an adequate EMI reduction. The measured EMI reduction of proposed SSCG is 14.37dB, where the RMS jitter is 1.49ps in locked mode and 1.49ps in spread mode. Also the peak-to-peak jitter is 13.33ps in locked mode and 19.90ps in spread mode.
The second chip is to implement the de-spreading technique, which regenerates a clock from a spread-spectrum clock reference without an extra crystal. The proposed crystal-less DSCG modulates the divided value of frequency synthesizer in order to cancel the spread-spectrum modulation, which is implemented by using a modulation frequency calibration and a triangular-wave phase delay calibration.
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