A Parallel Performance Analysis Framework for Cache Coherence Protocols

• Main Authors: Hui-Hsin Hsu, 許匯鑫
• Other Authors: Shih-Hao Hung
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/25583677656905128183

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 100 === Multi-core platform offer large performance potential for parallel software, but developing these softwares is very challanging. The performance of cache coherence protocol due to the data sharing in multi-threaded applications plays the important role that impacts the scalability. To analyze the cache performance in multi-core system, detail simulation can give the accurate results but it is too slow for complex systems since it serialized the simulation of many cores and the performance is bounded by the computation power of single core. In this thesis, we propose a novel multi-core cache performance analysis approach that combine the simualtion and analytic method fast performance estimation in parallel. The experimental results show that our approach performs about 13 times faster that the memory-access-based approach. We further integrate this parallel scheme into a parallel full-system emulator for system wide performance analysis but not only the user space applicaitons. To demonstrate the performance analysis framework, we show a case study that optimize a OpenMP program, the maximum performance improvement of the application is up to about 100\% under the configuration of using 16 OpenMP threads on our 48-cores host machine.