| Summary: | 博士 === 國立清華大學 === 奈米工程與微系統研究所 === 100 === This thesis based on the standard CMOS process and post CMOS metal wet-etching process to design and implement 3-axis CMOS-MEMS accelerometers. Typical CMOS-MEMS devices in academia typically adopted dry-etching process for structure geometry define and release. The design can only planar geometry and line width capabilities are restricted by the post CMOS process. This study proposed a design methodology using post CMOS metal wet-etching process. In addition to easily define the planar geometry, the undercut of metal layers is also achievable. Thus, higher design flexibility for CMOS-MEMS devices is achieved. Moreover, this process can fully utilize the CMOS line width to enhance the performance of CMOS-MEMS capacitive devices.
Firstly, a metal wet-etching based CMOS-MEMS in-plane and out-of-plane accelerometers are designed to verify the feasibility of this process. Using the small line width of CMOS process and the thickness of metal layer as capacitive sensing gap, the metal wet-etching based accelerometers have ultra-high performance compared with dry-etching ones. This study also proposed planar and vertical integration method to reduce the chip size. Planar integration design takes advantage of the line width ability to integrate the 3-axis sensing electrodes around the proof mass. Vertical integration method utilize the feature of multi-layer stacking of CMOS process to integrate the in-plane and out-of-plane sensing electrodes vertically. Moreover, the sensing scheme can still be the fully-differential and gap-closing sensing types. The structure area is significantly reduced but the number of sensing electrodes is still maintained.
|
|---|
