| Summary: | 碩士 === 國立清華大學 === 通訊工程研究所 === 100 === The next complete evolution in wireless communications, the fourth-generation (4G), becomes more competitive and intensive. The services of wireless communication applications demand for high data rate and high quality. Therefore, the communication applications in the future may demand for a higher speed channel coding scheme. The Turbo code is one of the most popular channel coding schemes for digital communication systems.
This thesis proposes a high–throughput variable-block-size Turbo decoder for 3GPPLTE-
Advanced system. This work increases the parallelism degree by the parallel subblock processing to achieve the high–throughput requirement. In addition, the proposed Turbo decoder supports 188 different block sizes in the range 40∼6144 for 3GPP-LTEAdvanced specification. Besides, the contention-free oriented memory remapping algorithm provides contention-free technique with any parallelism degree. Meanwhile, the compatibility with variable block size is also accomplished by the instruction-based interconnection circuit and pre-processed instruction ROM. Finally, the proposed variableblock-size Turbo decoder was implemented and the proposed design was synthesized with the 90nm UMC CMOS technology. The Turbo decoder has the throughput of 516Mb/s with 4 iteration loops, and energy efficiency is 0.2 nJ/bit/iter.
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