Time-Delay Integration Readout with Adjacent Pixel Signal Transfer for CMOS Image Sensor

• Main Authors: Cheng, Kuo-Wei, 鄭國韋
• Other Authors: Hsieh, Chih-Cheng
• Format: Others
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/97226898315482007337

碩士 === 國立清華大學 === 電機工程學系 === 100 === In the thesis, a time delay and integration (TDI) structure for CMOS image sensor (CIS) with adjacent pixel signal transfer (APST) is presented. The CCD-like TDI function is achieved in CIS by proposed APST without additional in-pixel device and routing effort. The in-pixel integrated signal is transferred to adjacent pixel and summed up by an off-pixel column-shared unity-gain buffer. There are several features of the proposed TDI structure. First, due to the column-shared unity-gain buffer utilized to transfer and readout signal, the power consumption and area occupancy are reduced and minimized greatly. Second, the proposed circuit has the advantage of CCD such as the ease of the summing signals with basic 3T APS pixel. There are proposed chips which are designed to compare and verify TDI function. A 128x6 APST TDI sensor with 6x6μm2 pixel size has been designed and fabricated in TSMC0.18μm 1P6M CIS technology providing 6 TDI stages with fill factor of 23.1%. The TDI function and the superior performance have been verified by experimental measurement with 3.3V power supply. It achieves a SNR improvement of 7dB with 6 TDI stages, a PRNU of 5.2%, and a low power consumption of 4.43uW/column which provides an optimized solution for remote sensing. Thanks to the column-shared op-amp adopted in this thesis, the chip size is minimized to 1.7mm x 1.3mm, and the transfer efficiency is also improved up to 99.6%. A 128x16 revised APST TDI sensor with 6x6μm2 pixel size has been designed and fabricated in TSMC0.18μm 1P6M CIS technology providing 16 TDI stages. The TDI function and the superior performance have been verified by experimental measurement with 3.3V power supply. It achieves a SNR improvement of 13dB with 16 TDI stages, a PRNU of 5.9%, and a low power consumption of 4.89uW/column. Thanks to the column-shared op-amp adopted in this thesis, the chip size is minimized to 1.7mm x 1.3mm.