| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 100 === Globally asynchronous locally synchronous (GALS) design is an efficient way to implement asynchronous systems. However, the locally synchronous (LS) modules with asynchronous wrappers make worst case performance. In order to achieve average case performance and facilitate asynchronous circuits design, this thesis proposes a general purpose wrapper that includes control circuits to cooperate with pausible clock controllers (PCC) and done circuits. The asynchronous wrappers using these circuits can wrap around not only synchronous blocks (with clock) but also combinational modules. The control circuits contain the write-port, read-port, and done-handling circuit. There are two implementations: one using standard cell library and the other using c-elements. The system using the former design can be implemented and verified conveniently using existing frond-end synchronous design flow. The latter is implemented for better performance, higher speed, smaller area and lower power consumption. Moreover, the proper ways of using the asynchronous wrappers for robust data communication in asynchronous systems are introduced. There are one-to-one, one-to-many and many-to-one communications. Users can use the wrappers to construct asynchronous systems such as GALS systems and asynchronous pipelines. Finally, the timing overhead of the asynchronous wrappers between local modules is analyzed. Guidelines for proper usage are also given.
|
|---|
