| Summary: | 碩士 === 國立清華大學 === 電子工程研究所 === 100 === This thesis presents an accurate dynamic analysis of Dickson Charge Pump that helps to realize how duty cycle affects the values of output voltage and voltage ripple. A Dickson Charge Pump with an automatic duty cycle control is also proposed. The designed circuit not only reaches the maximum output voltage under specific clock frequency but also decreases ripple by tuning the duty cycle. Therefore, its output voltage is more optimized than that of the conventional Dickson Charge Pump with 50% duty cycle.
In order to meet a wide range of application conditions, an external variable resistor is used to grossly adjust the clock frequency before the tuning of duty cycle sets in. For the circuit demonstrated in this thesis, the input voltage is 1.8V and an output voltage of 5V is obtained when the loading capacitance is 20pF and the loading current ranges from 0A to 50μA
The designed Dickson Charge Pump circuit was implemented in TSMC 0.18μm CMOS process, and its size is 1020×915μm2. The result of measurement shows that the dynamic control of duty cycle makes the circuit reach a maximum output voltage and the voltage ripple is smaller than that of-the fixed 50% duty cycle case.
|
|---|
