A Study of Single Contact RRAM and Its Vertical BJT Driver in Pure CMOS Logic Process

• Main Authors: Yang, Tsao-Hsin, 楊造鑫
• Other Authors: King, Ya-Chin
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/09519159844650351784

碩士 === 國立清華大學 === 電子工程研究所 === 100 === Flash memory is the only non-volatile semiconductor storage technology for mass production, and dominates the market of high-technology electronic products nowadays. However, flash memory suffers from many of challenges with scaling down, such as gate oxide leakage, soft breakdown, density limit, etc. For this reason, it is necessary to develop a new NVM, in order to pursue higher density, scalability and faster access speed. Resistive Random Access Memory has become the focus of many memory studies in recent years, it's a candidate as the next-generation NVM for the future, as a result of its strong advantages in scalability, non-volatility, endurance. Its simplicity as well as small size push RRAM device into the development of neuromorphic circuits, which simulates the functions and operations a brain. In this thesis, we propose a RRAM cell defined by a single contact area which named Single Contact RRAM (1C-RRAM). Utilizing contact resistive film as resistive switching element, driving and selecting by a novel vertical bipolar transistor underneath, hence 1C-RRAM can be further scaled to a small cell. In this study, we discuss the fabrication and architecture of 1C-RRAM, fabricated by 65nm CMOS logic process without any extra mask. In other words, this 1BJT+1R structure is fully CMOS-compatible. In addition, we investigate the layout of cell arrays and BJT characteristics in different technology; finally, 1C-RRAM has been successfully demonstrated by measurement result. We believe that 1C-RRAM is a very promising solution for future high density and embedded NVM applications.