TileSim+: A Parallel Trace-driven Simulator for NoC-based Cache-coherent CMP on TILERA 64
碩士 === 國立清華大學 === 資訊工程學系 === 100 === Chip Multiprocessor(CMP) is becoming the norm of processor chips. To design CMP, tracedriven simulation has been a commonly used technique for fast exploration of architecture design space. With the availability of parallel computers, such as Tilera’s Tile64, par...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48956765829863145720 |