TileSim+: A Parallel Trace-driven Simulator for NoC-based Cache-coherent CMP on TILERA 64

• Main Authors: Chiu, Yih-Nan, 邱奕楠
• Other Authors: King, Chung-Ta
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/48956765829863145720

碩士 === 國立清華大學 === 資訊工程學系 === 100 === Chip Multiprocessor(CMP) is becoming the norm of processor chips. To design CMP, tracedriven simulation has been a commonly used technique for fast exploration of architecture design space. With the availability of parallel computers, such as Tilera’s Tile64, parallel trace-driven simulation for faster architecture evaluation is becoming possible. However, there are very few papers discussing parallel trace-driven simulation. This thesis discusses the design and implementation of a parallel trace-driven simulator for NoC-based cache coherence CMP named TileSim+, TileSim+ provides cycle-accurate network model and cycle-count accurate cache simulation model, which allows the precise evaluation of memory access delay but exploration of cache design space for NoC-based CMP. Most importantly, accelerated with machine such as Tilera’s Tile64, TileSim+ speeds up trace-driven simulation with good scalability. The experimental evaluation of TileSim+ on TILE64 shows that it can obtain correct simulation results for the tested benchmark programs and achieve good speedup over sequential simulator. We also demonstrate how to use TileSim+ to evaluate CMP cache designs.