Implementation of x86 atomic instruction emulation in PQEMU

• Main Author: 王朝柱
• Other Authors: Chung, Yeh-Ching
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/75687993427119428751

碩士 === 國立清華大學 === 資訊工程學系 === 100 === QEMU for the Quick EMUlation abbreviation, it is a fast processor emulator, which has cross-platform features, and uses dynamic binary translation technology to improve the emulation efficiency. Nowadays, hardware devices are moving towards the era of multi-core machine, but the QEMU does not run in parallel, and therefore lost a multi-threaded parallel computing features in a multi-core machine. The PQEMU (multi-threaded QEMU) is designed for multi-core machines, and gains the advantages of multi-core processors. Its performance is average to 3.79 times faster than QEMU. PQEMU supports ARM instruction set architecture. The design proposed in this paper is the design of emulating the atomic instructions of x86 ISA. There are more than 18 atomic instructions in the x86 instruction set and it will be very complicated to design. The main idea of this design is due to the underlying ISA and the upper emulated ISA both are the x86 ISA, so it can apply one-to-one direct mapping to simulate the x86 atomic instructions. In order to evaluate the design, we emulate an x86 based machine on Intel core i7 quad-core hardware system and executes the simple and affective efficiency rating program. The experimental results show the effectiveness of one-to-one direct mapping emulation is average 34% faster than that of transactional memory approach.