A Study of High-Speed Non-Classical Unipolar CMOS with a Thick Sidewall-Spacer Gate-Oxide NMOS Load

• Main Authors: Shih-Wei Wang, 王識惟
• Other Authors: Jyi-Tsong Lin
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/92482272247593186456

碩士 === 國立中山大學 === 電機工程學系研究所 === 100 === In this thesis, we present a high-speed non-classical unipolar CMOS with a thick sidewall-spacer gate-oxide NMOS load. This unipolar CMOS is composed of a NMOS driver and a thick sidewall-spacer gate-oxide NMOS which replaces a PMOS as load. We focus on the investigation of punch-through current in unipolar CMOS trends. In addition, we also design a conventional CMOS for comparison. According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 20 % compared with the conventional CMOS. This is due to the presence of a thick sidewall-spacer gate-oxide NMOS load. For the viewpoint of device fabrication, the N well process can also be eliminated. This means that the proposed NMOS load not only improves the CMOS speed, but also reduces the fabrication cost. Thus, because of the shared-terminal output, the layout area can be significantly decreased 41 %, in comparison with the conventional CMOS.