Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain

• Main Authors: Mei-Na Tsai, 蔡美娜
• Other Authors: Ting-Chang Chang
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/64202508011271317122

博士 === 國立中山大學 === 物理學系研究所 === 100 === Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width and length, using high-κ gate dielectric insulator, and strained silicon may be utilized to increase the driving current and circuit speed. Nevertheless, the scaling of the channel width and length must overcome the limitation of the photolithographytechnology and cost. Once the method is employed, the MOSFETs will face a serious short-channel effect and gate leakage current. In the aspect of high-κ gate dielectric insulator, there still have problems, containing the trap states, phonon scattering, dipole-induced threshold voltage variation, needed to be solved. This dissertation focuses on the properties of MOSFETs experienced an external-mechanical strain, where the channel will be strained. Hence, the mobility, driving current, and circuit speed will increase. Our research can be divided into three topics: fabricating process-induced strained Si, external mechanical stress-induced strained Si, and the properties of strained Si MOSFETs at different temperatures. Except the electrical measurement, we also used the ISE-TCAD to simulate the electrical characteristic of MOSFETs under stress. Firstly, we apply the stress on n-MOSFETs by utilizing the nitride-capping layer. Once the lattice is strained, the mobility will increase, hence resulting in the operating speed. Secondly, the electrical characteristics under external stress is explored by introduced the external mechanical stress along the channel length of nMOSFETs. In addition to the fabricating process-induced strain, the fabricating process condition will also influence the device characteristics. As a result, we propose a new strain technology for our following research. Thirdly, the device performance of strained Si under different temperatures is investigated. Finally, we discuss the gate leakage current in strained Si depending on the ultra-thin gate oxide layer.