The Design of Low Power Dual-band / Wideband Low Noise Amplifier with Low Voltage
碩士 === 國立東華大學 === 電機工程學系 === 100 === The CMOS radio frequency (RF) circuits have been applied to portable biomedical equipment are presented in this thesis. There are two low noise amplifiers(LNA) design which are low power dissipation, low noise, frequency selection, bandwidth extension, and ga...
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/6n89gk |
| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 100 === The CMOS radio frequency (RF) circuits have been applied to portable biomedical equipment are presented in this thesis. There are two low noise amplifiers(LNA) design which are low power dissipation, low noise, frequency selection, bandwidth extension, and gain flatness improvement.
The first chip is a concurrent dual-band LNA(DBLNA). A band reject input matching network is used to achieve maximum power transfer. The operating frequencies are 0.9GHz and 2.45GHz. A folded circuit topology is used to reduce supply voltage. A forward body bias (FBB) technology is employed to ensure low supply voltage operation and to reduce total power dissipation.
The second chip is a wideband low noise amplifier (WLNA). The operating frequency is 0.9~3.5GHz. A band-pass input matching network is used. An inductor is placed between the input signal port and the first transistor to extend desired bandwidth. A complementary topology is used to boost gain and reduces noise performance. A FBB technique is used to ensure and to adjust gain boosting of complementary topology with low power consumption.
The proposed LNA chips are simulated by using Agilent circuit simulation software (Advanced Design System). The chips are layout by using SpringSoft circuit layout software (Laker). TSMC 0.18-um CMOS standard process is chosen to fabricate through CIC. The measurement of the front-end chip is done by using an on-wafer method.
The simulated results of the first chip (DBLNA) are as follow:
The supply voltage is 0.6(V). The power consumption is 4.76(mW). The input return loss (S11) are -13.5(dB) for 0.9GHz and -11.4(dB) for 2.45GHz. The output return loss (S22) are -13.7(dB) for 0.9GHz and -10(dB) for 2.45GHz.The forward transmission coefficient (S21) are 14.7(dB) for 0.9GHz and 10.1(dB) for 2.45GHz. The reverse transmission coefficient (S12) are -55.1(dB) for 0.9GHz and -47.3(dB) for 2.45GHz. The -1dB gain compression point (P-1dB) are -17(dBm) for 0.9GHz and -15(dBm) for 2.45GHz. The input third order intercept point(IIP3) are -24(dBm) for 0.9GHz and -16(dBm) for 2.45GHz. The noise figure are 4.5(dB) for 0.9GHz and 3.5(dB) for 2.45GHz.The chip area is 0.9 × 1.14mm2.
The simulated results of the second chip (WLNA) are as follow:
The DC supply voltage is 1V. The power consumption is 9.64mW. The input return loss (S11) is less than -10.55dBin the pass band. The output return loss (S22) is less than -10.23dB. The forward transmission coefficient (S21) is larger than 10.46dB. The reverse transmission coefficient (S12) is less than -72.02dB. The -1dB gain compression point (P-1dB) is -8.35dBm at 2.4GHz. The input third order intercept point(IIP3) is -8dBm at 2.4GHz. The noise figure is less than 3.3dB. The chip area is 0.98×0.91mm2.
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