Design of Asynchronous Fine-grain Power-gated Logic with Partial Charge Reuse
碩士 === 國立彰化師範大學 === 電子工程學系 === 100 === This thesis proposed a novel low-power logic circuit, called Asynchronous Fine-grain Power-gated Logic (AFPL). The AFPL logic adopts dual-rail encoding, and employs handshaking to transfer data between the adjacent modules. AFPL has the advantages of asynchrono...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65333041300406892247 |