| Summary: | 碩士 === 國立彰化師範大學 === 資訊工程學系 === 100 === In this article, using the TSMC 0.18um CMOS 1P6M Mixed Signal the process. Simulate the DC gain of up to 106.538 dB, bandwidth of up to 1.0623 GHz, while the phase margin can reach 64.88°, the power consumption of 3.6468 mW, the design for the wide swing of a high-gain low-power fully differential operational amplifier.
In this paper the design of high gain and low-power wide swing fully differential op amp to achieve a 12-bit pipeline analog-to-digital converter (pipeline ADC). This article will use the improved technology: single-stage 1.5-bit pipeline ADC, didital error correction (DEC), the double-sampling time-interleaved ADC. Through operational amplifiers, comparators sharing combination with each stage optimization capacitors, to achieve the purpose of high-speed conversion, low power consumption. According to simulation results, the power supply voltage of 1.8V, the sampling frequency of 200 MS / s, the input voltage range 2Vp-p, the input signal frequency of 1MHz, the power consumption for 44.75mW, differential nonlinearity (DNL) +0.4 ~ -0.36 LSB (least significant bit), integral nonlinearity (INL) +0.57 ~ -0.41 LSB.
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