An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit
碩士 === 國立中央大學 === 電機工程研究所 === 100 === The development and main stream of system-on-chip (SoC) are highly integration and higher operation speed. Therefore, in order to suppress the clock skew, the clock synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL)...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/70360223391225308906 |