| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 100 === In modern complex system-on-chip (SOC) designs, embedded random access memory (RAM)is a key component. A complex SOC typically contains a large number of RAM cores, and these cores usually occupy more than one half of the area of the SOC. Therefore, the yield of the SOC is dominated by the yield of RAM cores. Thus, effective yield-enhancement techniques are essential for RAM cores in SOCs. Built-in self-repair (BISR) technique has been acknowledged as one effective technique for improving the yield of embedded RAMs with redundancy.
A BISR circuit typically has a built-in redundancy-analysis (BIRA) module for allocating the redundancy. The efficiency of BIRA has heavy impact on the repair efficiency of the BISR circuit. In the first part of this thesis, we present a BIRA scheme for large RAMs with 3D redundancy (i.e., spare rows, spare columns, and spare IOs). The proposed BIRA scheme also can be designed as programmable such that it can serve multiple RAMs and support the multiple-time repair function to increase the repair rate further. Experimental results show that the proposed BISR scheme can achieve high repair rate and the area overhead of the proposed BIRA circuit for a 128K-bit RAM is only 2.83%.
In the second part of this thesis, two BIRA schemes with optimal repair rate for RAMs with 3D redundancy are proposed. One BIRA scheme using one analyzer to support multiple repair solutions is proposed to support the at-speed test and repair of word-oriented RAMs. Simulation results show that the area overhead of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA circuit is about 0.92% for a 2M-bit RAM with sixteen 8192×16-bit banks. To reduce the area cost further, a low-cost parallel BIRA design using one analyzer to support multiple repair solutions is proposed as well to reduce the area cost of the BIRA circuit, but it cannot perform the test and repair of RAMs at speed. Simulation results show that the low-cost BIRA scheme can reduce the hardware overhead of the proposed BIRA circuit to about 0.62% for a 2M-bit RAM with sixteen 8192×16-bit banks.
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