| Summary: | 碩士 === 國立中央大學 === 電機工程研究所碩士在職專班 === 100 === While reviewing the history of Taiwan''s semiconductor industry, the assembly and test technology of integrated circuit (IC) had been introduced to Taiwan for 40 years. Due to the government’s great support and lots of companies invested funds and human resource on the semiconductor industry over years, Taiwan has well developed the matured semiconductor technology including wafer process manufacturing, IC design, assembly and test infra-structure. Where the industrial structure is quite complete and their output value and growth rate are very significant.
The functions of IC become increasingly complex and powerful recently. In 1970s, from the operation frequency at megahertz (MHz) to gigahertz (GHz), therefore the IC product testing becomes important. From the product development cycle, testing costs (Cost of Test, COT) are becoming increasingly high. In order to meet the testing demand, due to IC product performance complexity and precision, then we require Automatic Test Equipment (ATE) with higher specifications relative to the investment of high COT.
The purpose of this paper is a test methodology to reduce the COT and increases the capacity of the final test (FT) production. The thesis contains the following section:
(1) Structure of the low COT ATE hardware and software
(2) Research of the testing capacity (productivity) enhancement and improve efficiency to reduce COT.
(3) Analog converter Digital’s (ADC’s) linearity innovation test based on "relationship between the pair of codes, RBPC" and its test program.
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