Qualification of the Array-Block-Capacitance Creator for Process Design Kit

• Main Authors: Ying-shang Chao, 趙盈勝
• Other Authors: Jwu-e Chen
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/11141562783984496058

碩士 === 國立中央大學 === 電機工程研究所碩士在職專班 === 100 === In Analog/Mixed-mode advance process, designer need use Process Design Kit to speed up the design flow and to enhance the success of product development. “Process Design Kit” is provided and verified by Foundry, it included the properties of the specified process, collecting the experience while process development, and integrate user’s request. “Process Design Kit” needs closer cooperation within Foundry and EDA vendor. In Analog/Mixed-mode circuit, we also need consider about the device matching to keep the performance of the circuit. But it’s not easy to predict and control the device matching while the devices in foundry’s process. Because the process variation affects the device character and reduces the device matching. We use Heuristic algorithm to get the placements, and find-out the optimal placement by considering the spatial correlation model which comes from Statistic. These procedures provided us a good solution, “Array-Block-Capacitance Creator”. By qualified our solution within PDK provider’s development flow and user’s design flow, we could embedded and used it in current PDK.