Soft-Decision BCH Decoder Design for NAND Flash Controller
碩士 === 國立交通大學 === 電機學院電機與控制學程 === 100 === This paper research background is the technology continues to scale down, the advantage of flash memory can reduce power consumption and cost of the hardware but the threshold voltage shift of one floating gate transistor can influence the threshold voltage...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82015413812529301963 |
| Summary: | 碩士 === 國立交通大學 === 電機學院電機與控制學程 === 100 === This paper research background is the technology continues to scale down, the advantage of flash memory can reduce power consumption and cost of the hardware but the threshold voltage shift of one floating gate transistor can influence the threshold voltage of its neighboring floating gate transistors through parasitic capacitance coupling effect in the flash memory. The traditional BCH decoder of hard decision can’t support to better efficient of decoding in the new manufacture. The purpose is based on the NAND flash specification of the 512 bytes transmission to design a chip of soft decision decoder. The soft decision used the tanner graph and iterations to search the maximum likelihood codeword. In the 2004, JN provide the new sorting concept in the procedure of soft decision of RS code. The purpose of JN could reduce error probability of the reliability exchange in the tanner graph after Gaussian Elimination. The paper would analysis and compares the soft decision structure to find suitable decoder on the decoding efficient and code length less than 512bytes. We decided the BCH-JN decoding of soft decision in the NAND flash. On the chip design, we based on the 0.18um to plan fix point value range to simulate and compare with real value simulation. In the hardware part, we analysis and compared their operation time and complex of the sorting 、Gaussian elimination and tanner graph circuit.
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