An Integrated Resistance Welding and TSV Process for Microsystems Packaging
碩士 === 國立交通大學 === 機械工程學系 === 100 === This paper proposes a novel wafer level packaging for integrated circuits (IC) and microelectromechanical system (MEMS) devices. In this method, two wafers were bounded by resistance welding with simultaneously through-silicon-via (TSV) connection and cavity seal...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86832757864743046678 |