Bootstrapped Circuit Techniques for Near-Subthreshold On-chip Data Link.

• Main Authors: Ho, Yingchieh, 何盈杰
• Other Authors: Su, Chauchin
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/31693117893779582946

博士 === 國立交通大學 === 電控工程研究所 === 100 === For the sustainable electronic devices, ultra-low power design is essential to prolong the battery lives. According to P = fCV2, scaling the supply voltage down is the most effective way to reduce the power consumption. According to the forecast from the International Technology Roadmap for Semiconductors (ITRS), the supply voltage will be scaled to 0.5V for low-power applications within the next generation. Scaling the supply voltage near the threshold voltage is the most favorable solution for low-power designs. On the other hand, Nano-scaled devices exceed the limit of the speed in the near-threshold region based on small device loading. Nano-scaled process is broadly applied to ultra-low power designs, which includes RF, AD/DA, MPU, especially in biomedical applications. Emerging embedded biomedical applications have once more pushed the low-power designs into another extreme case. In order to achieve the feature of the energy-efficient operation, the designs are applied to work using near-threshold supply. However, near-threshold circuit design is definitely challenging because the driving capability (Ion), which is limited to apply to slow system. Then, the static leakage power becomes severe, and decreases the Ion/Ioff ratio. Moreover, process variations are degraded significantly, affecting the circuit performance, the power efficiency, and the fabrication yield. In this dissertation, we propose circuit designs on-chip data link system using near-threshold supply. In order to improve the design issues in the near-threshold region, we have developed several bootstrapped circuits. The main contribution of the proposed bootstrapped techniques is to boost the gate voltage at the both sides, which means to boost the gate voltage of the PMOS and NMOS at the same time. The proposed circuit is applicable in both increasing driving ability by boosting signals into super-threshold region and reducing the leakage current. While the circuit is operated in sub-threshold region, two-order improvement is achieved. In addition, the bootstrapped circuits are operated in triode region with the near-threshold supply. Consequently, that explain why the process variation affects the proposed design scheme to a lesser extent. We can verify it with simulations of Monte Carlo analysis. Four build blocks using bootstrapped circuits in on-chip data link have been proposed. The first one is a bootstrapped CMOS inverter applied to on-chip clock network. In addition to improving the driving ability, a large gate voltage swing from -VDD to 2VDD suppresses the sub-threshold leakage current. The test chip is able to achieve 10MHz operation under 200mV VDD; the power consumption is 1.01μW. The Monte Carlo analysis results indicate that a sigma of delay time is only 2.9ns at 0.2V operation. Then, an ISI-suppressed bootstrapped repeater applied to on-chip bus is proposed. The bootstrapped CMOS repeaters are inserted to drive a 10mm on-chip bus. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. The measured results demonstrate that for a 10-mm on-chip bus, it can achieve 100Mbps data rate at 0.3V, and even 0.8 Mbps at 0.1V. The third section investigates the performance of the interconnects with repeater insertion in the sub-threshold region. A 3X CMOS pre-driver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. The measured results show that the 3X (4X) pre-drivers can achieve 5Mbps (1.5Mbps) data rate at 0.15V with an efficiency of 35.2fJ (32.8fJ). The last section, we present a near-threshold supply ADPLL with bootstrapped digitally-controlled ring oscillator (BDCO) that allows an ADPLL to operate with a near-threshold supply. The BDCO is composed of a bootstrapped ring oscillator (BTRO) and a weighted thermometer-controlled resistance network (WTRN). The proposed bootstrapped delay cell generates large gate voltage swing to improve the driving capability significantly. The boosted output swing keeps the transistors operated in the linear region to provide high linearity of the output frequency as function of VDD even using a near-threshold supply. According to the transferring character of the BTRO, WTRN provides linear control while sweeping the supply voltage. The proposed ADPLL oscillates from 36.8 to 480MHz with a power consumption of 2.4-78μW under a supply voltage of 0.25-0.5V.