Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth
碩士 === 國立交通大學 === 電控工程研究所 === 100 === In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed. The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a 3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented in TSMC 0.18 μm CMOS...
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87828643190952729608 |
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ndltd-TW-100NCTU54490152015-10-13T20:37:27Z http://ndltd.ncl.edu.tw/handle/87828643190952729608 Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth 20 MHz 訊號頻寬 640 MHz 連續時間三角積分類比數位轉換器設計 Hsu, Ming-Chao 許銘釗 碩士 國立交通大學 電控工程研究所 100 In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed. The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a 3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented in TSMC 0.18 μm CMOS process. The modulator operates at 640 MHZ clock frequency and the signal bandwidth is 20 MHz. The post simulated SNDR is 52.82dB and the dynamic range is 50dB. The power consumption is 20.5mW at 1.8V supply voltage. Tsai, Shang-Ho 蔡尚澕 2011 學位論文 ; thesis 60 en_US |
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NDLTD |
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en_US |
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Others
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NDLTD |
| description |
碩士 === 國立交通大學 === 電控工程研究所 === 100 === In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed.
The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a
3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented
in TSMC 0.18 μm CMOS process. The modulator operates at 640 MHZ clock
frequency and the signal bandwidth is 20 MHz. The post simulated SNDR is 52.82dB
and the dynamic range is 50dB. The power consumption is 20.5mW at 1.8V supply
voltage.
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| author2 |
Tsai, Shang-Ho |
| author_facet |
Tsai, Shang-Ho Hsu, Ming-Chao 許銘釗 |
| author |
Hsu, Ming-Chao 許銘釗 |
| spellingShingle |
Hsu, Ming-Chao 許銘釗 Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| author_sort |
Hsu, Ming-Chao |
| title |
Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| title_short |
Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| title_full |
Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| title_fullStr |
Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| title_full_unstemmed |
Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth |
| title_sort |
design of a 640 mhz continuous-time σδ adc with 20 mhz signal bandwidth |
| publishDate |
2011 |
| url |
http://ndltd.ncl.edu.tw/handle/87828643190952729608 |
| work_keys_str_mv |
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