Design of a 640 MHz Continuous-Time ΣΔ ADC with 20 MHz Signal Bandwidth
碩士 === 國立交通大學 === 電控工程研究所 === 100 === In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed. The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a 3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented in TSMC 0.18 μm CMOS...
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87828643190952729608 |
| Summary: | 碩士 === 國立交通大學 === 電控工程研究所 === 100 === In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed.
The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a
3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented
in TSMC 0.18 μm CMOS process. The modulator operates at 640 MHZ clock
frequency and the signal bandwidth is 20 MHz. The post simulated SNDR is 52.82dB
and the dynamic range is 50dB. The power consumption is 20.5mW at 1.8V supply
voltage.
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