A Theoretic Study on Three Low-Density Parity-Check and BCH Concatenated Coding Schemes

• Main Authors: Huang, Po-Yuan, 黃柏元
• Other Authors: Chen, Po-Ning
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/37821241941837457230

碩士 === 國立交通大學 === 電信工程研究所 === 100 === Bose-Chaudhuri-Hocquenghem (BCH) codes have been widely used in flash memories for many years. Yet, in future “high-density” multi-level cell (MLC) flash memories, the raw bit-error-rate (BER) in NAND flash may increase up to around 10−2 at its life time, and hence the conventional hard-decision ECC, such as BCH codes, is no longer sufficient for these memories. Hence, the low-density parity-check (LDPC) codes, as a class of powerful ECCs, become an important candidate for future MLC memories. One of the most significant impediments to the use of LDPC codes in future MLC flash memories is the error floor phenomenon associated with the iterative decoding. So in this thesis, we wish to realize whether the concatenated coding scheme of LDPC codes and BCH codes can eliminate or improve the error floor phenomenon of the LDPC code or not. We thus analyze in this thesis three BCH and LDPC concatenated coding schemes: (1) a single BCH code concatenates with multiple LDPC codes; (2) multiple BCH codes concatenate with a single LDPC code; (3) multiple BCH codes concatenate with multiple LDPC codes. Our analysis shows that the concatenation of the two codes can effectively lower the error floor of the LDPC-only code system at the price of a small rate loss.