Suppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generation

• Main Author: 顧鈞堯
• Other Authors: 溫宏斌
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/60809277023248582339

碩士 === 國立交通大學 === 電信工程研究所 === 100 === Multicore machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates concurrent interruption, ripple compaction and fault ordering to deal with the test-inflation problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fault ordering strategically arranges the fault list to reduce the number of test generations and speeds up the ATPG process. As a result, the proposed parallel ATPG system effectively reduces 11% pattern count with 0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits.