A Study on the Parallelism of Synchronous Ranked Neural Networks in CUDA System
碩士 === 國立交通大學 === 電信工程研究所 === 100 === In this thesis, we using the compute unified device architecture (CUDA) which NVIDIA announced a graphic processor unit (GPU) computing architecture to simulate the feature that synchronous ranked neural network (SRNN) can be updated synchronously. And aim at th...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75845188881895770189 |
| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 100 === In this thesis, we using the compute unified device architecture (CUDA) which NVIDIA announced a graphic processor unit (GPU) computing architecture to simulate the feature that synchronous ranked neural network (SRNN) can be updated synchronously. And aim at the SRNN operating feature, we discuss the effect of block update manner and neurons’ rank distribution on the amount of computation of SRNN convergence. We hope that we can aim at different SRNN handling problems to find some better setting for minimum computation. In the end, we use the packet scheduling of WDM OPAS-based optical interconnect system (WOPIS) problem as our SRNN model’s handling problem in block update manner. And prove the two effect factors that is as our expectation. In addition, we also want to find the best trade-off between the number of update block and execution parallelism by observing the execution efficiency in different parallelism.
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