| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 100 === With semiconductor fabrication technology developing, millions of standard cells and macros (pre-designed blocks or intellectual property (IP)) are integrated into a single chip. Legalization procedure is part of placement design in physical design automation. For a legal placement, all elements (cells and macros) are non-overlapping and all cells must be aligns to row. In this paper, we based on a method, HiBinLegalizer, which was published in ASPDAC-2010, proposed the grid bin size refinement and proved the solver for the objective function is optimal solution. The grid bin size refinement use the aspect ratio of macros to obtain the aspect ratio of grid and use the number of cells in maximum merged-bin to determine the bin size for HiBinLegalizer. Moreover, we proposed some lemmas to improve the procedure of trial row in HiBinLegalizer, so that, the order of time complexity is O(1) as compared with the original O(n) . The experimental results demonstrate the effectiveness of our method.
|
|---|
