A Discrete-time Complex Delta-Sigma A/D Converter with Time Division and Programmable Full-Scale for Wireline Application
碩士 === 國立交通大學 === 電信工程研究所 === 100 === With the rapid development of communication systems, there has been more focus on analog-to-digital converter (ADC). Among all of ADCs, delta-sigma converters have better trade-off between bandwidth and accuracy. The complex delta-sigma converter is one of the b...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04513214862675629324 |
| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 100 === With the rapid development of communication systems, there has been more focus on analog-to-digital converter (ADC). Among all of ADCs, delta-sigma converters have better trade-off between bandwidth and accuracy. The complex delta-sigma converter is one of the band-pass delta-sigma converters in the wireless communication system to solve the issue of imaginary signal injection into signal band during down conversion. Besides, complex system can achieve better noise suppression than real counterpart since the system pole/zero need not be formed as complex-conjugate pairs.
In this thesis, the design of the complex delta-sigma modulator will be presented.
Its feature of the asymmetric zeros about dc is applied for wireline application. Results show for a 500-kHz signal bandwidth the ADC achieves a dynamic range of 53dB and a peak signal-to-noise and distortion ratio of 37dB with an oversampling ratio of 6 (sample rate of 6.125MHz). It was fabricated in a TSMC 0.18-μm CMOS process with a 1.87 mm2 active area, and dissipates 35.6mW from a 1.8-V power
supply.
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