| Summary: | 博士 === 國立交通大學 === 電子研究所 === 100 === Energy efficient design is a key focus in emerging energy-constrained platforms. Dynamic voltage frequency scaling (DVFS) platform with energy-efficient designs are presented in this thesis. Ultra-low voltage temperature sensor and variation-aware clock generator are implemented to enable DVFS platform. Robust near-/sub-threshold SRAM/FIFO memories are designed as the test vehicle of DVFS platform.
An ultra-low voltage fully integrated frequency-domain smart temperature sensor is presented. With one-point calibration, a -1.81˚C~ +1.52˚C inaccuracy over a 0˚C~100˚C temperature operation range has been measured for 12 test chips. At a conversion rate of 45k samples/s, the proposed temperature sensor consumes an average power of 520nW and achieves 0.49˚C/LSB at 11-bit output resolution. It occupies only 990μm2 in a TSMC 65-nm general purpose bulk CMOS process. The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near-/sub-threshold region. Super-/near-/sub-threshold logical effort models are presented to eliminate delay estimation error caused by voltage and temperature variations. A near-/sub-threshold programmable clock generator is also presented in this thesis. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the lock-in range of clock generator to guarantee successful clock lock. In addition, it has the ability to generate the output clock with frequency from 1/8 to 4 times of the reference clock. The clock generator has been designed using UMC 65nm CMOS technology. The frequencies of reference clock are 625 KHz at 0.2V and 5MHz at 0.5V. The power consumptions are 0.18μW and 5.17μW, respectively, at 0.2V and 0.5V. The core area of this clock generator is 0.01mm2.
A 9T SRAM bit-cell is presented to enhance write ability by cutting off the positive feedback loop of SRAM cross-coupled inverter pair. In read mode, an access buffer is designed to isolate storage node from read path for better read robustness and leakage reduction. Bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit-cell with additional write-wordlines (WWL/WWLb) for soft error tolerance. A 1Kbit 9T 4-to-1 bit-interleaved SRAM is implemented in 65nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3V supply voltage. It can achieve an operation frequency of 909kHz with 3.51μW active power consumption. An ultra-low power (ULP) 16Kbit SRAM-based first-in first-out (FIFO) memory is also presented for wireless body area networks (WBANs). The proposed FIFO memory is capable of operating in ultra-low voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell is proposed to be the storage element for improving write variation in ULV regime and eliminate the data-dependent bit-line leakage. The proposed SRAM-based FIFO memory also features adaptive power control circuit, counter-based pointers, and a smart replica read/write control unit. The proposed FIFO is implemented to achieve a minimum operating voltage of 400mV in UMC 90nm CMOS technology. The write power is 2.09μW at 50kHz and the read power is 2.25μW at 625kHz.
Finally, a 512-word by 16-bit (8kb) subthreshold asynchronous first-in first-out (FIFO) memory is presented for wireless body area networks (WBANs). Meanwhile, A 1kb dynamic voltage scaling 8T SRAM-based FIFO memory is implemented to operate between 0.5V (near-threshold) and 0.3V (subthreshold) in UMC 65nm technology with 0.535μW at 625kHz and 0.163μW at 20kHz power consumption, respectively. The proposed DVS FIFO memory can provide up to 69.5% power savings when low-power mode is always engaged, and there is no power overhead if the period of low-power mode is longer than 48.66μs. It is suitable for healthcare applications equipped with DVFS capability.
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