| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === Phase noise is an important factor, which is used to estimate the performance of phase locked loop, and the choice of the bandwidth could also affect the phase noise directly. In an analog phase-locked loop, the bandwidth depends on the current of charge pump, the passive components in the loop filter and the gain of voltage control oscillator (VCO). Unfortunately, they would differ from the designed values because of the process, voltage and temperature (PVT) variation. However, in an all-digital phase-locked loop, the bandwidth is composed of some well-known parameters and the gain of digital control oscillator (DCO), but only the gain of DCO is unpredictable because of the PVT variation.
An all-digital fractional-N frequency synthesizer with background calibration is presented. The background calibration method of the DCO gain could relieve the PVT variation on the DCO gain without affecting the operation of the communication system at the same time. Adding a digital code at the input of the DCO, so that the output of loop filter would generate an opposite signal,able to be recorded to formulate the estimation of the DCO gain. The background calibration method of the DCO gain could restore the loop bandwidth without changing other loop parameters.
Besides, jitter performance is another important factor, which is used to estimate the performance of phase-locked loop. But it is difficult to measure the output clock jitter of the high speed phase-locked loop circuit directly. In addition, using external measuring equipment takes the high cost. For the reasons, the on-chip jitter measurement method, which dumps the frequency tuning word from the input of DCO, could estimate the jitter performance by lower frequency. Since the measured frequency changes from output frequency to reference frequency level, the on-chip jitter measurement methodcould release the cost of equipment.
Implemented in TSMC-40nm CMOS technology, the total area included PAD is 1.330 x 1.195mm2. The measured output frequency of proposed ADPLL is 8GHz, where the RMS jitter is 3.4251ps in integer-N architecture and 13.019ps in fractional-N architecture.
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