| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === With the growing computation-intensive requirement for multimedia and communication applications, the functional units need to work under high clock frequency. Therefore, how to improve the performance of the functional units to enable the design operating in the high-speed and high-performance computing has become the major issue in the current circuit design.
The speculating design reduces the computing length of the critical path and this will cause computing error; therefore, the compensating value is speculated by the mathematical analysis to reduce the error probability. We divided the functional unit into two parts and computed them in parallel for reducing the critical path delay and increasing the performance. However, this method will induce the functional unit computing error owing to some computations which are unable to finish computing on time. The concept of variable-latency design is to fast the common case. And when these cases occurring, we only need one cycle to compute; in contrast, when the worst cases occurring, we need another cycle to recover the computing error and this will causing the degenerated performance. Therefore, we propose the variable-latency design which is realized by the speculating method and error recovery mechanism. Furthermore, the technologies of carry estimation are applied to increasing the computing accuracy in the first cycle of the functional units.
This thesis analyzed the partition of the function units and the proposed method of carry estimation. By the cost function of performance exploration, we can find the most optimal (high-performance) design parameters which is the trade-off between clock cycle time and the accuracy. In here, the clock cycle time means the tightest timing of critical path need in the design. To shorten the cycle time can improve the performance in design. The accuracy means those cases can be finished in one cycle. The rest of the cases need additional cycles to recover the result and this will degenerate the performance. According to these analyses, the high-performance and variable-latency functional unit is implemented.
In our simulations, we adapted several multi-media applications: the object of the human faces detection and the discrete cosine transform (DCT) to demonstrate the improved ratio of the performance in our proposed design. As compared with conventional design methodology and other currently available researches, the proposed design can improve 20.9% ~ 21.9% of performance ratio. The speed in our design can run 47.42% faster than the pipeline design under the same synthesis timing constraint when data hazard occurred. When compare with the pipeline design under the same performance, the area in our design can be reduced 4.20% and the power consumption can be reduced 24.02%.
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