| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === More and more memory is used in today’s electronic products, and consequently the design of memory is becoming crucial. SRAM is usually used in high-performance microprocessor cache and embedded system applications because it has highest operating speed than other memory family. Conventional 6T SRAM use “thincell” layout to achieve high density, so it becomes the mainstream of SRAM design. However, with recently CMOS technology scaling, the greatest barrier to achieving high yield is process variation. The process variation is especially serious for high density SRAM because of the small device size and large capacity. This will seriously degrade the SRAM cell operating margin in advanced technology node. In the low-voltage operation, the conventional 6T SRAM is almost impossible to survive.
For the 6T SRAM in the advanced process, in order to promote the survival probability, we proposed Read/Write assist circuit techniques. The proposed Step-Up Word-Line technique improves Read Static Noise Margin with acceptably loss of read speed and Write margin. The Write ability and Write performance are enhanced by a column based Adaptive-Data-Aware Write-Assist scheme. We also use Pipeline scheme to increase the operating speed. In this work, we implement a 1.0Mb high-performance 6T SRAM with 2 stages Pipeline with a single supply voltage in the 40nm Low-Standby-Power bulk complementary metal-oxide semiconductor technology. The chip can operate across wide voltage range from 1.2V to 0.7V, with operating frequency of 800MHz@1.2V and 25oC.
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