Efficient Hardware Implementation of Eta_T Pairing in Characteristic Three

• Main Authors: Wu Jing-Yu, 吳靜瑜
• Other Authors: Chang, Hsie-Chia
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/03098625135494581127

碩士 === 國立交通大學 === 電子研究所 === 100 === In this thesis, we implement the reduced η_T pairing algorithm in characteristic three over supersingular elliptic curve. The algorithm involves additions, multiplications, cubing, and inversion over F_(3^m ) and does not need any cube root. The implementation of the Miller’s algorithm utilizes the composite field arithmetic associated to the η_T pairing. We also propose an enhancement for final exponentiation, which is still required to obtain a unique value of bilinear pairing in the extension fields F_(3^6m ). We propose two efficient hardware implementations, one is a serial approach and the other one is a pipeline approach. The first one utilizes 3 multipliers over F_(3^m ) computing a single iteration of Miller’s algorithm in 6 stages. However, each iteration takes 54 clock cycles and the overall algorithm takes 54*49 clock cycles. Since Miller’s algorithm dominates the computation time of pairing algorithm, we propose an enhancement for Miller’s algorithm so that a single iteration of which is reduced to 17 clock cycles. Because the overall computation time of Miller’s algorithm is decreased to 17*49 clock cycles, which is almost the same as the one of final exponentiation, these two major components can compute in a pipeline manner. From UMC 90 nm technology, the first approach can achieve 200 MHz with only 163.6K gate-count and the computation time is 18.6 μs according to post-layout simulation result. For the other one, the computation time is only 3.33 μs on 250 MHz with 336K gate-count according to synthesis result.