Power Integrity for TSV 3D Integration

• Main Authors: Yang, Po-Jen, 楊博任
• Other Authors: Hwang, Wei
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/56664866806400415887

碩士 === 國立交通大學 === 電子研究所 === 100 === In this thesis, a hierarchical power delivery system is proposed for the power integrity of through-silicon-via (TSV) 3D integrations using various noise reduction techniques. The proposed hierarchical power delivery system decouples the global power network and the local power networks not only for reducing the required decoupling capacitors (DECAPs) but providing flexible power sources. For achieving the further power noise reduction both in the global and local power networks, an active switching DECAPs and adaptively biased low dropout regulators are adopted as the global regulator and local regulators, respectively. Additionally, a substrate noise suppression technique is also presented to enhance the power integrity by reducing both substrate and TSV coupling noises. Moreover, a design methodology for area-efficient power TSV planning is proposed to optimize the area-occupancy and voltage drop performance. The simulation results of a heterogeneous TSV 3D integration demonstrate that the noise reduction on power supply pairs (VDD + GND) are suppressed by up to 71.10% with only 1.11% power overhead based on the proposed hierarchical power delivery system. Therefore, the proposed hierarchical power delivery system is very useful for the power integrity of the heterogeneous integration in TSV 3D-ICs.