| Summary: | 博士 === 國立交通大學 === 電子研究所 === 100 === Ultra-Thin-Body (UTB) Si and Ge-channel MOSFETs (such as UTB Silicon-On-Insulator (SOI), Germanium-On-Insulator (GeOI), and FinFET devices) are viable options for future CMOS technology owing to the superior short-channel control and inherent low device variability due to undoped channel. However, in spite of the extensive research on the device characteristics of these emerging devices, there has not been much analysis from the circuit-level perspective. The goal of this dissertation is to investigate and analyze how these emerging device structures (such as UTB GeOI, UTB SOI and FinFET devices, etc.) impact the leakage, performance, stability and variability of logic circuits and SRAM cells, and provide insights for UTB GeOI, SOI and FinFET devices/circuits design.
First, we assess the electrostatic integrity for nano-scale UTB Ge-channel MOSFETs with various buried insulator permittivity (such as GeOI and Germanium-On-Nothing (GeON)) by using a derived analytical solution of Poisson’s equations that may provide scalable and predictive results for our analysis of UTB GeOI and GeON MOSFETs devices. Based on the investigation of electrostatic integrity for UTB GeOI MOSFETs, we analyze the leakage-delay, stability and variability of UTB GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts comprehensively. The UTB GeOI circuits show better power-performance than the Bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of Bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better 𝝁RSNM/σRSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V compared with the SOI SRAM cells.
We have also conducted research on the UTB SOI SRAM cells operating in the subthreshold region including the investigation of stability, performance, leakage and variability for 6T/8T UTB SOI subthreshold SRAM cells. An analytical framework to calculate the Static Noise Margin (SNM) for UTB SOI subthreshold SRAM cells is presented to efficiently investigate the Read/Write stability (RSNM/WSNM). The results indicate that for both the RSNM and WSNM improvement, the back-gating technique is more effective in the subthreshold mode than in the superthreshold mode. The impact of threshold voltage design on the UTB SOI SRAM cells operating near the subthreshold region is also investigated. The lower threshold voltage devices operating slightly into superthreshold region improve the stability/variability significantly and offer higher performance for ultra-low voltage SRAM applications. The intrinsic advantages of UTB SOI technology versus Bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are also demonstrated. The RSNM of UTB SOI subthreshold SRAM cells show smaller variability and less temperature sensitivity compared with that of Bulk subthreshold SRAMs. Due to the very small subthreshold swing fluctuations, Work Function Variation (WFV) shows less impact on the variability of UTB SOI subthreshold SRAMs, and the variability of UTB SOI subthreshold SRAMs is dominated by Line-Edge Roughness (LER). Our results indicate that the 6T UTB SOI subthreshold SRAM cells with back-gating technique and threshold voltage design may adequately meet/support the stability, leakage/density, and frequency requirements for intended application space of subthreshold SRAMs.
In addition to the intrinsic process variation, we demonstrate that the negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations change the optimal choice of FinFET SRAM cell surface orientations in term of the μ/σ ratio in RSNM. The combined effects of time-zero intrinsic process variability and long-term temporal variability (due to NBTI/PBTI) are considered for optimizing the FinFET device orientation combinations to improve the stability/variability of 6T FinFET SRAM cells with oxide and high-K gate dielectrics, respectively. We also investigate the 6T FinFET SRAM cells using asymmetric gate-to-source/drain underlap device to improve RSNM without degrading WSNM, and the resulting impacts on performance and variability. The conflict between improving RSNM and WSNM in 6T FinFET SRAM cell can be relaxed by using the asymmetric source/drain underlap access and pull-up transistors.
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