| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === As technology for lithography beyond 65nm, the IC industry faces challenge in reliability. Many resolution enhancement technologies (RETs) have been developed to improve yield and reliability. For these patterns which are susceptible to lithography process, if designer can avoid generate them, it can improve this problem. In general, this problem is called “pattern matching”.
In this thesis, we propose a DRC based topological analysis algorithm. By analyzing topological relation of this pattern, we can convert topological properties to DRC rules. Then, these rules apply to DRC checker to pre-filter the potential positions of patterns. Finally, we will do exact pattern matching to these potential positions. By our algorithm, we can efficiently and accurately to identify all the positions of hotspots. These positions will be reported to designer to correct the layout for improving yield.
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