| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === H.264/MPEG-4 AVC scalable extension can provides high compression efficiency and high visual quality with spatial, temporal, quality scalabilities for diverging decoding terminals. However, this also significantly increases the design complexity, particularly for real time high definition video encoding.
This thesis proposes a fast two step intra prediction algorithm and its hardware design to meet real time demands. The first step is the intra block size decision by distinguishing the block smoothness through selected AC coefficients. The second step is a transform based mode candidates for 4x4 block and merged 4x4 mode candidates for 8x8 block. The experimental results shows that we can save more than 80% candidate modes, with similar quality (average BD-PSNR difference: -0.01 dB for CIF, +0.12dB for 1080p, average BD-Rate difference: +0.01% for CIF, -3.13% for 1080p), when compared with JM full search method. The resulted hardware design shares single prediction units for different block size computation and interleaved computes two macroblocks to avoid data dependency with embedded quality layer processing in the reconstruction loop. The implementation with 90nm CMOS process costs 148k gate counts, and 17.9k bytes SRAM buffer under 135MHz operating frequency to support processing rate of three quality layers, three spatial layers (CIF, SD 480p and HD 1080p) and up to 60 frames per second.
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