On Constructing Low Power and Robust Clock Tree
碩士 === 國立交通大學 === 電子研究所 === 100 === Timing check is a critical stage in clock tree synthesis (CTS). Since no previous work has addressed on accurate timing model and most related works perform skew optimization by embedding SPICE simulation process into CTS flow, we should have more efficient timing...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00447693781120674184 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === Timing check is a critical stage in clock tree synthesis (CTS). Since no previous work has addressed on accurate timing model and most related works perform skew optimization by embedding SPICE simulation process into CTS flow, we should have more efficient timing check during CTS. To improve the run time and achieve the goal of minimizing power under all constraints, we propose a novel two-stage methodedology based on Elmore delay model and timing independent method. First, several sub-trees with similar delay under slew constraint are generated. Then we construct a top-level symmetrical tree that considers buffer sizing and wire-length minimization. Our approach not only significantly reduces the number of SPICE simulations, but also provides a high tolerance of variation and low power consumption.
Experimental results are evaluated from the benchmarks of ISPD contest 2010. The proposed technique reduces 58% of power consumption on average and significantly improves the run time compared with the first place of the ISPD contest 2010.
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