| Summary: | 博士 === 國立交通大學 === 電子研究所 === 100 === Wireless body area network (WBAN) is an emerging technology which is specifically designed for body signal collection and monitoring to provide reliable physical information. In order to achieve long duration monitoring for biotelemetry applications, the WBAN system is required to provide reliable signal transmission, ultra-low power operation, and highly integrated tiny area for comfortable purposes.
This dissertation first introduces a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). The baseband transceiver chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 ?巰.
From the system power analysis, the power dominant of the proposed WBAN solution is the active power of the wireless transmission link, especially the power amplifier (PA) due to the poor efficiency. Accordingly, linear amplification by nonlinear components (LINC) is introduced to improve the amplifier efficiency. The basic concept is to separate the original phase-and-amplitude modulated signal into two phase-only-modulated signals, then these two signals can be amplified by high-efficiency nonlinear PAs. Then the desired signal can be reconstructed by combining these two amplified signals. This dissertation focuses on the signal component separator (SCS) design. An all-digital phase-modulated SCS architecture, including the phase calculation DSP and a digitally-control phase shifter (DCPS) pair, is proposed in this work to avoid the usage of DACs and quadrature modulators. Besides, this SCS design also considers the branch mismatch issue and presents a digital mismatch detection and compensation scheme, which can be integrated in the SCS without increasing the front-end circuit complexity. The proposed SCS design is manufactured in 90 nm standard CMOS process. The overall SCS operating at maximum 100 MHz consumes less than 1 mW which minimizes the power overhead of the LINC transmitter, and it further provides a 0.02 dB gain and 0.15o phase fine-tune resolution to release the front-end design complexity.
Besides, the uneven multi-level LINC (UMLINC) is introduced for further efficiency improvement. Assuming the PA can provide dual gain mode, the efficiency can be improved from 13.08% to 44.82% (3.44x improvement comparing to LINC). The branch mismatch consideration is also considered during the region boundaries decision of the signal separation. An all-digital SCS chip, which provides the PA gain controls and corresponding phase-modulated signals for UMLINC systems, is manufactured in 90 nm standard CMOS process. By applying the voltage scaling and low power techniques, the power cost of UMLINC SCS is only 0.65 mW. With the proposed UMLINC SCS, 80.23% transmitter power can be reduced comparing to conventional transmitter with a linear PA. Applying this technique to the proposed WBAN system, the average system power can be reduced from 1626 μW to 518 μW for MT-CDMA mode and from 211 μW to 132 μW for OFDM mode respectively.
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