| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 100 === Chip, package, and board are nowadays designed separately and then combined into one system by their interfaces. The interfaces have become much more complex as the number of input/output (IO) pins increases. Few commercial EDA tools provide effective support. Since the problems caused by interfaces involve many design decisions such as time-to-market (TTM) and productivity, and it is not easy to formulate, some practical and efficient interfacing methods are strongly in need to facilitate chip/package/system designs.
On the other hand, iterative re-works with package houses and RDL trial routing exist in conventional design flow. Accordingly, from design houses' point of view, co-design with package houses and good RDL router must be developed to enable fast implementation of RDL. Our proposed algorithms for chip-package-board interfacing contain two parts.
The first work is RDL routing on pseudo single-layer which targets at congested cases where 100\% routability cannot be achieved within single layer. Our approach can achieve 100\% routability and minimize the area for 2-layer routing on a real industrial case, outperforming a state-of-the-art commercial RDL router. The second work contains the methodologies which can generate package pin-out and wire planning for chip-package-board co-design. It provides wire planning without time-consuming routing process to estimate package size, signal integrity, and routability.
Our approaches can enable fast re-spin between chip, package, and system design houses.
Through these two works, design houses can greatly reduce the design efforts and time-to-market.
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