Design and Implementation of Reconfigurable Memory Architecture for MIMO Wireless Applications

• Main Author: 丁張玉
• Other Authors: 許騰尹
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/54620837032053614571

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === This thesis proposes and implements a reconfigurable memory system for multiple-input and multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) system for wireless application. By utilizing the signal processing operations and hardware requirements are quite similar among different antenna branches in MIMO-OFDM system, the feature is used to implement software controlled wireless communication platform which can execute variety specification without re-design the hardware architecture. The concept of reconfigurable is applied in the proposed memory system of this thesis which makes the memory can process different amount and format of data without re-design the system architecture. The proposed reconfigurable memory system can support two type of wireless communication specifications, long term evolution (LTE) and IEEE 802.11ac, three kinds of antenna number (1, 2, 4) and 1024 FFT points in LTE specification is provided in the proposed platform. And the support mode of 802.11ac specification is four kinds of antenna number (1, 2, 4, 6) and three kinds of FFT point (128, 256, 512). The architecture of this system is divided into two parts, one is data flow management (DFM) and on-demand memory, another is the concept of scheduling is used in data flow management to deal with the large amount of continuous input data stream. The software parameter is used to select the scheduling to finish the data process in different specification with fixed hardware. In the part of on-demand memory, the distribution memory for each data process module is collected into a centralize memory system to reduce the memory cost and increase the benefit of dynamic memory allocation. The virtual address and dynamic memory allocation is used to improve the scalability of memory system in this work. And the minimum of allocated memory size is a single word (32 bits) which makes the memory allocation is more flexible and lower the probability of the fragment to raise the memory Utilization. This thesis provides architecture which combines the above two parts and uses the method of scheduling and the dynamic allocation to implement the reconfigurable memory system.