Register Allocation Techniques for GPU Shader Processors

• Main Authors: Chen, Szu-Chieh, 陳思捷
• Other Authors: You, Yi-Ping
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/92001701099712636174

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === Graphics processing units (GPUs) have been widely used in embedded systems for manipulating computer graphics and even for general-purpose computation. However, many embedded systems have to manage limited hardware resources to achieve high performance or energy efficiency. The number of registers is one of the common limiting factors in an embedded GPU design. Programs that run with limited registers may suffer from high register pressure if register allocation is not properly designed, especially on a GPU in which a register is divided into four elements and each element can be accessed separately because allocating a register to a vector-typed variable that does not contain values in all elements creates a waste of register spaces. In this thesis we present a vector-aware register allocation framework to improve register utilization on shader architectures, thereby reducing register spills. The framework involves two major components: (1) element-based register allocation that allocates registers upon the element requirements of variables and (2) register packing that rearranges elements of registers in order to make more contiguous free elements for keeping more live variables in registers. Experiments demonstrated that the proposed register allocation decreases a mean of 92% of register spills and results in more reduction in energy consumption (from 1.7% to 4.7%) than a previous work that applied a power-control mechanism to the output buffer, where a register is spilled to.