Leveraging Adaptive Set-Configurable Architecture to Reduce Conflict Misses of PCM Last-Level Cache in CMP
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === As the number of cores in a chip is increased, last-level caches (LLC) play an important role in latency gap between processor cores and main memory. Bandwidth limitation becomes a bottleneck to limit many-core scaling, since off-chip memory bandwidth grows...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/97790486966623061724 |